1. Field
The present invention relates generally to mixed signal simulation and verification systems, and more particularly to preparing a mixed signal design for simulation or verification.
2. Description of Related Art
Digital designers have worked for years with digital description languages, such as VHDL and Verilog. Likewise, analog designers have worked for many years with analog description languages, such as SPICE. More recently, due to the increasing need for mixed-signal Computer Aided Design (CAD) tools, mixed signal versions of simulation tools have become more prevalent. For example, mixed signal versions of Verilog and VHDL presently exist, which enable simulation of portions of a design with either or both of analog and digital simulation tools.
These mixed-signal description languages and associated simulation tools provide for simulating portions of a design as logic or as an analog circuitry. For example, Verilog-AMS provides the concepts of a domain and a discipline that may be assigned to interconnects (nets). In Verilog-AMS, the domain may either be analog or digital (i.e., continuous or discrete), and determines whether a given net is to be simulated using a digital simulation tool or an analog simulation tool. Disciplines, in addition to specifying a domain, may include other attributes, for example, measurement units for voltage levels. Thus, assigning a discipline to a net also defines a domain for the net, and thereby determines whether that net should be simulated as an analog or a digital net. After nets are assigned disciplines, it is possible to define digital/analog partitions using automated algorithms, wherein digital islands comprise interconnected nets that have been assigned a digital discipline, and analog islands comprise interconnected nets that have been assigned an analog discipline.
In Verilog-AMS, to demarcate such partitions before simulation, a transition between an analog island and a digital island is marked by a Connection Module (CM). In addition to bridging analog and digital, CMs bridge portions of a design having different characteristics such as voltage level shifts, bus widths, etc. CMs may be automatically inserted or may be inserted by a user. Currently, before CMs can be automatically inserted, nets need to have an assigned discipline (i.e., information as to whether each net is to be simulated as analog or digital must be known).
Verilog-AMS provides an automated process called “discipline resolution” that determines what discipline to assign each net in a design. The discipline resolution process generally proceeds as defined by the standard. Users may also, on a net-by-net basis designate an analog or a digital discipline for nets.
After discipline resolution, a design may be partitioned by insertion of CMs. For example, partitions in the design can be identified by determining which analog nets connect with each other to form an analog island, and which digital nets connect with each to form a digital island. The boundaries between the digital islands and the analog islands are the partitions in the design. The simulator tool will insert CMs at each net that crosses a given partition.
Sometimes, these partitions comport with what the user would have selected had a choice been made by the user. And sometimes, especially for users who may be unfamiliar with AMS, this discipline resolution process produces unexpected results, because some of the nets may have been assigned an analog discipline, when the designer wanted the net to be digital, or vice versa. In other words, the discipline of nets and subsequent partitioning of the design by the tool was not as the user would have desired.
For example, during design verification, verification personnel may assemble blocks, some digital and some analog, of a semiconductor design provided by a number of different designers. These designers may have not have provided disciplines for the nets in their blocks before providing them to verification. In some cases, these blocks may have first been designed with tools that did not have a domain concept, because they were either pure analog or digital tools. For these cases, the verification personnel may either manually modify the design of each block by specifying what domain (or discipline) should be assigned to each net, or the designer may run the tool and allow the tool to automatically determine where to insert CMs to specify how each net should be simulated. If the verification personnel modified the design to specify disciplines on nets, then the design has then been changed by the verification personnel and there needs to be some coordination with the designer of that block to ensure that there is coherency in the design. Where the tool automatically determined the disciplines of nets, the verification personnel would typically review the automatically assigned domains and change (coerce) those that were incorrectly determined. This process can be tedious, especially for nets that cross various blocks in a design.